View IDT74LVC823A_679556.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

IDT74LVC823A 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
* 0.5 MICRON CMOS Technology * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static) * Rail-to-rail output swing for increased noise margin * All inputs, outputs, and I/O are 5V tolerant * Supports hot insertion * Available in SSOP, QSOP, and TSSOP packages
IDT74LVC823A
FEATURES:
DESCRIPTION:
DRIVE FEATURES:
* High Output Drivers: 24mA * Reduced system switching noise
APPLICATIONS:
* 3.3V high speed systems * 3.3V and lower voltage computing systems
The LVC823A 9-bit bus-interface flip-flop is built using advanced dual metal CMOS technology. The LVC823A device is designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, latching the outputs. This device has noninverting data (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to go low, independently of the clock. A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. OE does not affect internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state. The LVC823A has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment.
FUNCTIONAL BLOCK DIAGRAM
OE CLR CLKEN
1 11 14
CLK
1D
13 2
R
C1
1D
23
1Q
TO EIGHT OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c) 2004 Integrated Device Technology, Inc.
JANUARY 2004
DSC-4608/2
IDT74LVC823A 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM TSTG Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VO < 0 Continuous Current through each VCC or GND -0.5 to +6.5 -65 to +150 -50 to +50 -50 100
Unit V C mA mA mA
OE
1D 2D 3D 4D 5D 6D 7D 8D 9D
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
VCC
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q
IOUT IIK IOK ICC ISS
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT CI/O Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 4.5 5.5 6.5 Max. 6 8 8 Unit pF pF pF
NOTE: 1. As applicable to the device type.
CLR GND
CLKEN CLK
PIN DESCRIPTION
Pin Names Description Output Enable Input (Active LOW) Clock Input Clock Enable Input (Active LOW) Clear Input (Active LOW) Data Inputs Data Outputs OE CLK CLKEN CLR xD xQ
SSOP/ QSOP/ TSSOP TOP VIEW
FUNCTION TABLE (EACH FLIP-FLOP)(1)
Inputs OE L L L L H CLR L H H H X CLKEN X L L H X CLK X X X xD X H L X X Outputs xQ L H L Q(2) Z
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH transition 2. Output level before indicated steady-state input conditions were established.
2
IDT74LVC823A 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL IOFF VIK VH ICCL ICCH ICCZ ICC High Impedance Output Current (3-State Output pins) Input/Output Power Off Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 0V, VIN or VO 5.5V VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC -- -- -- -- -- -- -- -0.7 100 -- -- -- 50 -1.2 -- 10 10 500 A V mV A VCC = 3.6V VO = 0 to 5.5V -- -- 10 A Parameter Input HIGH Voltage Level Input LOW Voltage Level Input Leakage Current VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VI = 0 to 5.5V Test Conditions Min. 1.7 2 -- -- -- Typ.(1) -- -- -- -- -- Max. -- -- 0.7 0.8 5 A V Unit V
Quiescent Power Supply Current Variation
3.6 VIN 5.5V(2) One input at VCC - 0.6V, other inputs at VCC or GND
A
NOTES: 1. Typical values are at VCC = 3.3V, +25C ambient. 2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2.2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
3
IDT74LVC823A 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, VCC = 3.3V 0.3V, TA = 25C
Symbol CPD CPD Parameter Power Dissipation Capacitance per Flip-Flop Outputs enabled Power Dissipation Capacitance per Flip-Flop Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 59 46 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.7V Symbol fMAX tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ tW tW tSU tSU tSU tH tH tSK(o) Parameter Propagation Delay CLK to xQ Propagation Delay CLR to xQ Output Enable Time OE to xQ Output Disable Time OE to xQ Pulse Duration, CLR LOW Pulse Duration, CLK HIGH or LOW Set-up Time, CLR inactive before CLK Set-up Time, data before CLK Set-up Time, CLKEN LOW before CLK Hold Time, data after CLK Hold Time, CLKEN LOW after CLK Output Skew(2) 3.3 3.3 1 1.3 1.8 2 1.3 -- -- -- -- -- -- -- -- -- 3.3 3.3 1 1.3 1.8 2 1.3 -- -- -- -- -- -- -- -- 1 ns ns ns ns ns ns ns ns -- 7.1 1.1 6 ns -- 8.3 1.6 7.2 ns -- 8.8 2.5 7.9 ns Min. 150 -- Max. -- 8.9 VCC = 3.3V 0.3V Min. 150 1.4 Max. -- 8 Unit MHz ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC823A 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50 6 2.7 1.5 300 300 50 VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30 Unit V V V mV mV pF
SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL
VIH VT 0V VOH VT VOL VIH VT 0V
LVC Link
VCC 500 Pulse (1, 2) Generator VIN D.U.T. RT 500 CL VOUT
VLOAD Open GND CONTROL INPUT
Propagation Delay
ENABLE DISABLE VIH VT 0V VLOAD/2 VOL+VLZ VOL VOH VOH-VHZ 0V
LVC Link
tPZL OUTPUT SWITCH NORMALLY VLOAD LOW tPZH OUTPUT SWITCH NORMALLY GND HIGH VLOAD/2 VT tPHZ VT 0V
tPLZ
LVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 10MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 10MHz; tF 2ns; tR 2ns.
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL VIH VT 0V VOH VT VOL VOH VT VOL
tSU
tH
tREM
tSU
tH
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
LVC Link
INPUT
Set-up, Hold, and Release Times
tPLH1
tPHL1
OUTPUT 1
tSK (x)
tSK (x)
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
VT
OUTPUT 2 tPLH2 tPHL2
VT
Pulse Width
LVC Link
LVC Link
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVC823A 3.3V CMOS 9-BIT BUS-INTERFACE FLIP-FLOP
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
X LVC IDT XX Bus-Hold Temp. Range XX XXXX Device Type Package
PY Q PG 823A Blank 74
Shrink Small Outline Package Quarter Size Small Outline Package Thin Shrink Small Outline Package
9-Bit Bus-Interface Flip-Flop with 3-State Outputs, 24mA No Bus-hold -40C to +85C
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
6

▲Up To Search▲

Price & Availability of IDT74LVC823A

	To Download IDT74LVC823A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .